In the field of semiconductor blocks, several factors must typically be balanced when designing and manufacturing integrated circuits (ICs) for use in various applications. Among these factors are circuit complexity, operation speed, substrate real estate and the diversity of tasks the IC may be called upon to handle. All of these have a potential impact on overall manufacturing cost. Ideally, designers and manufacturers seek ICs having the smallest substrate real estate, yet operate the fastest and are the least complex in design. Practically, however, as one desirable characteristic is optimized, another characteristic suffers.
For example, application specific integrated circuits (ASICs) are extremely fast at the tasks they are designed to handle. Generally speaking, ASICs are constructed by designing a circuit for specific operations, and then forming only the necessary semiconductor blocks (in the desired layout) on a substrate, as well as the customized interconnects needed among the blocks, to accomplish the desired tasks. Because the circuitry employed (both blocks and interconnects) is tailored to specific operations, ASICs typically occupy only that amount of substrate real estate needed to accomplish its goals. Unfortunately, the speed and small real estate achievable with ASICs come at the expense of their post-design flexibility. Since ASICs are designed with specific tasks in mind, their ability to handle tasks outside their design is very limited, if present at all.
At the other end of the spectrum are field programmable gate arrays (FPGAs). FPGAs are constructed by forming standard layouts of semiconductor blocks on a substrate, but then allowing the interconnection of these blocks to be programmable as the need arises. In this manner, FPGAs are reprogrammable in the “field,” depending on the desired operation to be performed. However, the flexibility of the FPGAs comes at the expense of both speed and real estate. More specifically, since the tasks for which an FPGA will be used in not predetermined, a sufficient number of semiconductor blocks (forming logic gates) must typically be formed to allow the FPGA to perform a variety of operations. In addition, although a relatively large number of blocks are formed in the FPGA, not all the blocks are used for each task; thus, unused blocks often occupy valuable space no matter what task is being performed. Furthermore, since the block layout is not tailored for specific tasks, many blocks may have to be employed to perform the same function that a lesser number of blocks in a custom designed ASIC could. As a result, the speed of FPGAs typically suffers as a greater number of blocks are required to perform a desired operation.
Lying between ASICs and FPGAs are programmable gate arrays (PGAs). PGAs are constructed by forming standard semiconductor block layouts on a substrate, similar to FPGAs. However, the layout of the interconnects for the blocks is typically customized for desired operations. Thus, PGAs provide lower manufacturing costs than ASICs, due primarily to the use of standard block layouts instead of custom designed layouts, and faster speed than FPGAS, due to the customized dedicated interconnect structures. Unfortunately, since tasks-specific interconnects are employed, PGAs still suffer from the limited number of tasks they may perform. Moreover, with a PGA, if minor defects are found in the final IC die, a new interconnect layout must typically be created, and new dies manufactured, to overcome the defects. In view of the costs associated with creating new interconnect layer reticles and constructing new IC dies, manufacturers are understandably eager to find an alternative logic block having the desired flexibility. This is especially the case in those situations where the defects affect block performance, but perhaps not enough to warrant the expense and delay associated with the construction of new reticles and new IC dies.
Accordingly, what is needed in the art is logic block that does not suffer from the deficiencies typically found in conventional logic block designs.